Combinatory logic for multi-level memory cells
AssigneeMicron Technology, Inc.
InventorsDaniele Vimercati, Veeresh Salimath, Shuai Xu
Life of this patent
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Abstract
A memory device includes first combinatory logic configured to receive multiple-digit representations of stored voltage values from each of N respective memory cells in a first memory array, and each of the memory cells is configured to store a charge having one of at least three different charge levels. The first combinatory logic can provide a first multiple-bit word, based on the received multiple-digit representations of the stored voltage values, and a number of bits in the first multiple-bit word is greater than N.
Claims20
A memory device comprising:
- first combinatory logic configured to:
- receive multiple-digit representations of stored voltage values from each of N respective memory cells in a first memory array, wherein each of the memory cells is configured to store a charge having one of at least three different charge levels;
- and
- based on the received multiple-digit representations of the stored voltage values, provide a first multiple-bit word, wherein a number of bits in the first multiple-bit word is greater than N.
A memory device comprising:
- first combinatory logic configured to:
- receive two-digit representations of stored voltage values from N respective memory cells in a memory array, wherein each of the memory cells is configured to store a charge having one of at least three different charge levels;
- and
- based on the received two-digit representations of the stored voltage values, provide an M-bit word, wherein M is the nearest and least integer to a result of the function log2(3^N).
A method for selecting a number of memory cells to use together to provide a multiple-bit word, the method comprising:
- for each of multiple integer values of N:
- determining a theoretical maximum number of bits that can be stored using N memory cells, wherein each of the memory cells is configured to store more than one bit and less than two bits of information;
- determining an actual number of bits available from the N memory cells;
- and
- determining an utilization characteristic of using the N memory cells based on a relationship between the actual number of bits available from the N memory cells and the theoretical maximum number of bits that can be stored using the N memory cells;
- and selecting a value of N that maximizes the utilization characteristic.
Dependencies are inferred from the claim text.