Gate driving circuit and display device including gate driving circuit

A gate driving circuit, comprising:

• first and second dummy stage circuits that are each capable of supplying a carry signal and each comprise a Q node, a QH node, and a QB node;
• and
• a plurality of stage circuits that are each capable of supplying gate signals to each gate line and each include the Q node, the QH node, and the QB node,
• wherein each of the plurality of stage circuits is configured to supply a respective gate signal to a corresponding gate line among a plurality of gate lines based on at least one of a plurality of clock signals from first and second dummy stage circuits, one or more preceding stage circuits among the plurality of stage circuits, and one or more following stage circuits among the plurality of stage circuits;
• and
• wherein the first dummy stage circuit is configured to be activated by a start signal, generate a first preceding stage carry signal, and output the first preceding stage carry signal to the second dummy stage circuit and a first stage circuit among the plurality of stage circuits, and
• wherein the second dummy stage circuit includes a Q node configured to control charging or discharging of the Q node based on the first preceding stage carry signal.

A gate driving circuit, comprising:

• first and second dummy stage circuits that each includes a Q node, a QH node, and a QB node;
• and
• a plurality of stage circuits that each includes a Q node, a QH node, and a QB node,
• wherein each of the plurality of stage circuits is connected to supply a respective gate signal to a corresponding gate line among a plurality of gate lines based on at least one of a plurality of carry signals from the first and second dummy stage circuits, one or more preceding stage circuits among the plurality of stage circuits, and one or more following stage circuits among the plurality of stage circuits, and
• wherein the first dummy stage circuit is configured to be activated by a start signal to output a carry signal and the second dummy stage circuit is configured to be activated by the carry signal from the first dummy stage signal.