Selective implementation of a redundant array of independent nand procedure

A method, comprising:

• receiving, by a memory system controller and from a host system, host data to be written to a portion of a non-volatile memory associated with a memory system;
• determining, by the memory system controller and for the host data, a first set of parity information that is associated with a first redundant array of non-volatile memory devices procedure;
• determining, by the memory system controller, whether the portion of the non-volatile memory is associated with a second redundant array of non-volatile memory devices procedure different from the first redundant array of non-volatile memory devices procedure;
• and
• performing one of:
• determining, by the memory system controller and for the host data, a second set of parity information that is associated with the second redundant array of non-volatile memory devices procedure when it is determined that the portion of the non-volatile memory is associated with the second redundant array of non-volatile memory devices procedure;
• or
• forgoing, by the memory system controller, determination of the second set of parity information when it is determined that the portion of the non-volatile memory is not associated with the second redundant array of non-volatile memory devices procedure.

A memory system, comprising:

• one or more components configured to:
• receive data to be written to a portion of a memory;
• determine, for the data, a first set of parity information that is associated with a first redundant array of independent memory procedure;
• determine whether the portion of the memory is associated with a second redundant array of independent memory procedure different from the first redundant array of independent memory procedure;
• and
• perform one of:
• determining, for the data, a second set of parity information that is associated with the second redundant array of independent memory procedure when it is determined that the portion of the memory is associated with the second redundant array of independent memory procedure;
• or
• omitting determination of the second set of parity information when it is determined that the portion of the memory is not associated with the second redundant array of independent memory procedure.