US 2026/0029960 A1 · LOGICAL ADDRESS INDICATIONS FOR ACCESSING SEQUENTIAL DATA FROM A MEMORY SYSTEM

Abstract

Methods, systems, and devices for logical address indications for accessing sequential data from a memory system are described. The described techniques provide for a memory system to access sequential data associated with non-contiguous logical address ranges based on receiving a read command including information indicating the non-contiguous logical address ranges. For example, the read command may indicate the non-contiguous logical address ranges in an extra header segment (EHS) data field and the memory system may use the indication of the non-contiguous logical address ranges to improve access performance, such as by informing a pre-reading algorithm. In some examples, the memory system may identify that the EHS data field includes a logical address table based on one or more second fields of the read command, such as an EHS length field, an EHS type field, and an EHS sub-type field.

Claims24

Dependent claims

A memory system, comprising:

one or more memory devices;
and
processing circuitry coupled with the one or more memory devices and configured to cause the memory system to:
receive a read command indicating a first set of one or more logical addresses and a second set of one or more logical addresses that is non-contiguous with the first set of one or more logical addresses, the first set of one or more logical addresses and the second set of one or more logical addresses associated with a set of sequential data;
access at least one of the one or more memory devices at a plurality of physical addresses corresponding to the first set of one or more logical addresses and the second set of one or more logical addresses to retrieve the set of sequential data in response to the read command;
and
output the set of sequential data in accordance with accessing the at least one of the one or more memory devices.

4 more elements

A non-transitory computer-readable medium storing code comprising instructions which, when executed by processing circuitry of a memory system, cause the memory system to:

receive a read command indicating a first set of one or more logical addresses and a second set of one or more logical addresses that is non-contiguous with the first set of one or more logical addresses, the first set of one or more logical addresses and the second set of one or more logical addresses associated with a set of sequential data;
access one or more memory devices of the memory system at a plurality of physical addresses corresponding to the first set of one or more logical addresses and the second set of one or more logical addresses to retrieve the set of sequential data in response to the read command;
and
output the set of sequential data in accordance with accessing the one or more memory devices.

1 more element

Dependencies are inferred from the claim text.

Logical address indications for accessing sequential data from a memory system

Life of this patent

Logical address indications for accessing sequential data from a memory system

Life of this patent

Abstract

Claims24