Independent parallel plane access to improve bootup latency in a multi-plane memory device
AssigneeMicron Technology, Inc.
InventorsDeping He, Xing Wang, Qisong Lin
Life of this patent
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Abstract
A memory sub-system includes a memory device comprising a memory array comprising a plurality of planes a processing device configured to detect a boot process of the system subsequent to an occurrence of a power loss event, and initiate a series of multi-plane read operations to identify a last written page of the memory device, wherein the last written page was programmed prior to the occurrence of the power loss event, and wherein at least a portion of the memory device remains unprogrammed.
Claims20
A system comprising:
- a memory device comprising a memory array comprising a plurality of planes;
- and
- a processing device, operatively coupled with the memory device, to perform operations comprising:
- detecting a boot process of the system subsequent to an occurrence of a power loss event;
- and
- initiating a series of multi-plane read operations to identify a last written page of the memory device, wherein the last written page was programmed prior to the occurrence of the power loss event, and wherein at least a portion of the memory device remains unprogrammed.
A method comprising:
- detecting a boot process of a memory sub-system subsequent to an occurrence of a power loss event, the memory sub-system comprising a memory device comprising a plurality of planes;
- and
- initiating a series of multi-plane read operations to identify a last written page of the memory device, wherein the last written page was programmed prior to the occurrence of the power loss event, and wherein at least a portion of the memory device remains unprogrammed.
A non-transitory computer-readable storage medium storing instructions which, when executed by a processing device, cause the processing device to perform operations comprising:
- detecting a boot process of a memory sub-system subsequent to an occurrence of a power loss event, the memory sub-system comprising a memory device comprising a plurality of planes;
- and
- initiating a series of multi-plane read operations to identify a last written page of the memory device, wherein the last written page was programmed prior to the occurrence of the power loss event, and wherein at least a portion of the memory device remains unprogrammed.
Dependencies are inferred from the claim text.