Digital biasing and digital cell placement technique for semiconductor packaging

A method comprising:

• conducting a metrology scan to determine a pillar height and a pillar critical dimension for each of a plurality of non-uniform pillars disposed over a die, the metrology scan generating metrology data corresponding to the pillar heights and the pillar critical dimensions of the plurality of non-uniform pillars, the metrology data generating a compensated mask pattern;
• conducting a digital lithography process according to the compensated mask pattern to form a plurality of vias, the vias are formed over each non-uniform pillar of the plurality of non-uniform pillars and include a via depth and via critical dimension;
• and
• conducting a solder plating process, the solder plating process filling each via in the plurality of vias with a solder bump, each solder bump secured to one non-uniform pillar of the plurality of non-uniform pillars.

A non-transitory computer-readable medium storing instructions that, when executed by a processor, cause a computer system to perform the steps of:

• receiving metrology data, the metrology data corresponding to pillar heights and pillar critical dimensions, wherein a digital lithography system including a controller is operable to update a mask pattern, the mask pattern corresponding to a pattern of uniform pillars;
• updating the mask pattern according to the metrology data to generate a compensated mask pattern based on the pillar heights and the pillar critical dimensions;
• and
• conducting a digital lithography process to pattern on a resist according to the compensated mask pattern to form a plurality of vias, the vias are formed over each non-uniform pillar of a plurality of non-uniform pillars and include a via depth and a via critical dimension after the resist is developed.