Built in self-test of heterogeneous integrated radio frequency chiplets

An electronic assembly for built-in self-test of a chiplet assembled in a heterogeneous process, the assembly comprising:

• an area of host wafer having a first circuit including a plurality of wafer transistors and a plurality of wafer passive, non-transistor devices;
• a chiplet having a second circuit including a radio frequency (RF) chiplet transistor;
• electrical interconnects between the chiplet and wafer, wherein the electrical interconnects electrically connect the first circuit to the second circuit;
• and
• an oscillator having the plurality of wafer transistors, the radio frequency (RF) chiplet transistor and the electrical interconnects, wherein the oscillator is included in a built-in self-test circuit for testing an assembly design of the electronic assembly based on the gain and/or speed of the radio frequency (RF) chiplet transistor.

A method of forming an electronic assembly having built-in self-test of chiplets, the method comprising:

• bonding a host wafer having a first circuit including a plurality of wafer transistors and a plurality of wafer passive, non-transistor devices to an encapsulation layer;
• bonding a plurality of chiplets having a second circuit including at least one radio frequency (RF) chiplet transistor to the encapsulation layer;
• forming electrical interconnects between the chiplets and wafer, wherein the electrical interconnects electrically connect the first circuit to the second circuit;
• and
• forming a plurality of oscillators each having some of the plurality of wafer transistors, the at least one RF chiplet transistor of a chiplet and some of the electrical interconnects, wherein each oscillator of the plurality of oscillators produces a signal for the built-in self-test circuit for testing an assembly design of the electronic assembly and a speed of the at least one RF chiplet transistor of the chiplet.