Virtualizing Hardware Processing Resources in a Processor

A processing arrangement comprising:

• an interface configured to receive work commands specifying work and virtual identifiers of respective processors;
• a work distributor structured to distribute the specified work to the respective processors based on the received work commands and virtual identifiers;
• and
• a mapper structured to map between the virtual identifiers and logical and/or physical identifiers associated with the respective processors.

A process of declaring processing capabilities of an integrated circuit comprising:

• defining a multi-processor Cooperative Group Array Region consisting of the union of non-defective processors per cluster of a population of integrated circuits;
• defining processors that can support Singletons within the population of integrated circuits;
• and
• assigning virtual hardware identifiers at least to the processors that can support Singletons.

A non-transitory memory device coupled to a processor, the memory device storing:

• a Skyline declaring virtual GPC IDs assigned to corresponding processing hardware clusters, wherein at least one of the processing hardware clusters comprises a Singleton;
• and
• instructions that when executed by the processor control the processor to perform operations comprising:
• (a) testing an integrated circuit;
• (b) comparing results of the testing with the stored Skyline;
• and
• (c) configuring the integrated circuit in response to the testing and the comparing to selectively disable hardware processors not needed for the integrated circuit to provide processing capabilities the Skyline declares.