Semiconductor device and method of fabricating the same

A semiconductor device, comprising:

• a substrate including a first active pattern and a second active pattern, which are spaced apart from each other in a first direction parallel to a top surface of the substrate;
• a device isolation layer between the first and second active patterns;
• a first source/drain pattern disposed on the first active pattern;
• a second source/drain pattern disposed on the second active pattern;
• a first active contact disposed on the first and second source/drain patterns;
• a barrier pattern interposed between the first active contact and the first source/drain pattern and between the first active contact and the second source/drain pattern;
• and
• an air gap interposed between the first active contact and the barrier pattern,
• wherein the first active contact comprises:
• a first body portion on the first active pattern;
• a second body portion on the second active pattern;
• and
• a third body portion on the device isolation layer,
• wherein the air gap is interposed between the third body portion and the device isolation layer.

A semiconductor device, comprising:

• a substrate including a first active pattern and a second active pattern, which are spaced apart from each other in a first direction parallel to a top surface of the substrate;
• a device isolation layer between the first and second active patterns;
• a first source/drain pattern disposed on the first active pattern;
• a second source/drain pattern disposed on the second active pattern;
• a first channel pattern disposed on the first active pattern and connected to the first source/drain pattern;
• a second channel pattern disposed on the second active pattern and connected to the second source/drain pattern;
• a first active contact disposed on the first and second source/drain patterns;
• a barrier pattern interposed between the first active contact and the first source/drain pattern and between the first active contact and the second source/drain pattern;
• and
• an air gap interposed between the first active contact and the device isolation layer,
• wherein each of the first and second channel patterns comprises a plurality of semiconductor patterns, which are spaced apart from each other in a second direction perpendicular to the top surface of the substrate, and
• the first active contact is electrically connected to the first and second source/drain patterns.