Semiconductor device

A semiconductor device comprising:

• a first semiconductor structure having a memory region;
• and
• a second semiconductor structure, in contact with the first semiconductor structure, the second semiconductor structure having a peripheral circuit region vertically overlapping the memory region,
• wherein the first semiconductor structure includes:
• a memory structure including a vertical channel transistor disposed in the memory region, and an information storage structure disposed on the vertical channel transistor;
• a cell routing line structure disposed below the vertical channel transistor, the cell routing line structure electrically connected to the memory structure;
• a cell bonding structure disposed below the cell routing line structure;
• a cell hydrogen supply layer, surrounding a portion of the cell routing line structure, between the cell bonding structure and the vertical channel transistor, the cell hydrogen supply layer including a first insulating material;
• and
• a cell insulating layer, surrounding at least a portion of the vertical channel transistor, on the cell hydrogen supply layer, the cell insulating layer including a second insulating material, different from the first insulating material, and
• wherein the second semiconductor structure includes:
• peripheral circuits disposed in the peripheral circuit region;
• a peripheral routing line structure electrically connecting the peripheral circuits and the cell routing line structure to each other;
• and
• a peripheral bonding structure disposed on the peripheral routing line structure, the peripheral bonding structure in contact with the cell bonding structure.

A semiconductor device comprising:

• a first semiconductor structure having a memory region;
• and
• a second semiconductor structure, in contact with the first semiconductor structure, the second semiconductor structure vertically overlapping the first semiconductor structure, the second semiconductor structure having a peripheral circuit region vertically overlapping the memory region,
• wherein the first semiconductor structure includes:
• a memory structure including a vertical channel transistor disposed in the memory region, and an information storage structure disposed on the vertical channel transistor;
• and
• a cell routing line structure electrically connected to the memory structure,
• wherein the second semiconductor structure includes:
• a peripheral circuit disposed in the peripheral circuit region;
• and
• a peripheral routing line structure electrically connecting the peripheral circuit and the cell routing line structure to each other,
• the first semiconductor structure further includes a cell hydrogen supply layer, surrounding a portion of the cell routing line structure, between the vertical channel transistor and the second semiconductor structure, and
• the second semiconductor structure further includes a peripheral hydrogen supply layer surrounding a portion of the peripheral routing line structure.