Memory device with inter-layer dielectric regions

A memory device, comprising:

• a plurality of chips comprising a first chip, a second chip, and a third chip, the plurality of chips being sequentially stacked,
• wherein a memory cell array is disposed in the first chip,
• wherein a second sub-peripheral circuit region is disposed in the second chip,
• wherein a first sub-peripheral circuit region is disposed in the third chip, and
• wherein a thickness of a first lowermost inter-layer dielectric (ILD) region of the first sub-peripheral circuit region is different from a thickness of a second lowermost ILD region of the second sub-peripheral circuit region.

A memory device, comprising:

• a cell region in which a memory cell array is disposed;
• and
• a peripheral circuit region at least partially vertically overlapping the cell region,
• wherein the peripheral circuit region comprises:
• a first sub-peripheral circuit region;
• and
• a second sub-peripheral circuit region at least partially vertically overlapping the first sub-peripheral circuit region,
• wherein the first sub-peripheral circuit region comprises a first transistor region and a second transistor region,
• wherein the second sub-peripheral circuit region comprises a third transistor region and a fourth transistor region, and
• wherein thicknesses of first lowermost ILD regions of transistors disposed in the first transistor region and the second transistor region are different from thicknesses of second lowermost ILD regions of transistors disposed in the third transistor region and the fourth transistor region.