Semiconductor chip and semiconductor package including the same

A semiconductor chip comprising:

• a semiconductor substrate;
• a through silicon via that vertically penetrates the semiconductor substrate;
• an integrated device layer on a first surface of the semiconductor substrate and comprising integrated devices;
• a multi-wiring layer on the integrated device layer and comprising layers of wires;
• an upper metal layer on the multi-wiring layer and connected to an uppermost wire of the multi-wiring layer through a via contact, the upper metal layer being on an upper metal layer area of the first surface of the semiconductor substrate;
• an upper bump pad on an upper bump area of the first surface of the semiconductor substrate;
• a lower bump pad on a lower bump area of a second surface of the semiconductor substrate;
• and
• a lower metal layer on a lower metal layer area of the second surface of the semiconductor substrate, the lower metal layer area being on a periphery of the lower bump area,
• wherein the lower metal layer comprises a material having a coefficient of thermal expansion (CTE) greater than a CTE of the semiconductor substrate, and
• wherein the lower metal layer is shaped as one of:
• a plate, a serpent, a plurality of metal pads, or a plurality of metal lines.

A semiconductor package comprising:

• a first semiconductor chip;
• and
• at least one second semiconductor chip stacked on the first semiconductor chip, wherein the at least one second semiconductor chip comprises:
• a semiconductor substrate;
• a through silicon via that vertically penetrates the semiconductor substrate;
• an integrated device layer on a first surface of the semiconductor substrate and having integrated devices;
• a multi-wiring layer on the integrated device layer and comprising layers of wires;
• an upper metal layer on the multi-wiring layer and connected to the wires;
• bump pads on a lower bump area on a second surface of the semiconductor substrate;
• and
• a lower metal layer on the second surface of the semiconductor substrate,
• wherein the lower metal layer is on a periphery of the lower bump area, and
• wherein the at least one second semiconductor chip is stacked such that a first surface of the at least one second semiconductor chip faces the first semiconductor chip.