Back to results
US 2026/0018522 A1Published application
Apparatus and method for fabricating multi-die interconnection using lithography process
AssigneeCerebras Systems Inc.
InventorsJean-Philippe Fricker, Philip Ferolito
Life of this patent
Estimating the term…
Abstract
A semiconductor and a method of fabricating the semiconductor having multiple, interconnected die including: providing a semiconductor substrate having a plurality of disparate die formed within the semiconductor substrate, and a plurality of scribe lines formed between pairs of adjacent die of the plurality of disparate die; and fabricating, by a lithography system, a plurality of inter-die connections that extend between adjacent pair of die of the plurality of die.
Claims20
A semiconductor device comprising:
- a substrate;
- a plurality of processing elements (PEs) disposed on the substrate in an arrangement such that a subset of the plurality of PEs is disposed at a periphery of the arrangement;
- a plurality of inter-PE connections extending between and coupling respective pairs of PEs of the plurality of PEs;
- and
- a plurality of peripheral connections that is distinct from the plurality of inter-PE connections, wherein the plurality of peripheral connections is formed at one or more sides of one or more respective PEs of the subset along the periphery of the arrangement.
2 more elements
A method comprising:
- forming a plurality of processing elements (PEs) on a substrate in an arrangement such that a subset of the plurality of PEs is disposed at a periphery of the arrangement;
- forming a plurality of inter-PE connections extending between and coupling respective pairs of PEs of the plurality of PEs;
- and
- forming a plurality of peripheral connections that is distinct from the plurality of inter-PE connections, wherein the plurality of peripheral connections is formed at one or more sides of one or more respective PEs of the subset along the periphery of the arrangement.
1 more element
Dependencies are inferred from the claim text.