Semiconductor structure including isolation elements with etching-resistant upper portions and method for manufacturing the same

A method for manufacturing a semiconductor structure, comprising:

• forming a first conducting layer on a base structure;
• forming a trench in the first conducting layer, such that the first conducting layer is formed into first conducting portions spaced apart by the trench;
• filling the trench with a mixture including a dielectric material and an etching-resistant material which is at least partially soluble in the dielectric material and which is different from the dielectric material;
• performing a treatment to permit segregation of the mixture, such that the dielectric material constitutes a dielectric lower portion, and such that the etching-resistant material constitutes an etching-resistant upper portion covering the dielectric lower portion and being exposed from the first conducting portions;
• sequentially forming an etch stop layer and an interlayer dielectric over the first conducting portions and the etching-resistant upper portion;
• forming a cavity which extends through the etch stop layer and the interlayer dielectric, and which exposes one of the first conducting portions;
• and
• filling the cavity with a second conducting portion.

A semiconductor structure, comprising:

• a base structure;
• a lower interconnect level formed on the base structure, and including
• first conducting portions;
• and
• isolation elements, each of the isolation elements isolating two adjacent ones of the first conducting portions from each other, each of the isolation elements including a dielectric lower portion and an etching-resistant upper portion covering the dielectric lower portion, a surface energy of the etching-resistant upper portion being lower than a surface energy of the dielectric material;
• and
• an upper interconnect level formed on the lower interconnect level opposite to the base structure, the upper interconnect level including
• an etch stop layer and an interlayer dielectric that are sequentially formed over the lower interconnect level;
• and
• a second conducting portion that penetrates through the etch stop layer and the interlayer dielectric, and that is connected to one of the first conducting portions.