Memory built-in self-test (mbist) for a memory expansion of a high-bandwidth memory (hbm) device

A semiconductor device comprising:

• a substrate;
• a processor assembled onto the substrate;
• a high-bandwidth memory (HBM) device assembled onto the substrate, the HBM device comprising:
• one or more memory dies;
• and a logic die on which the one or more memory dies are assembled, the one or more memory dies comprising:
• an HBM physical layer (PHY) coupled with the processor and the one or more memory dies;
• a die-to-die interface separate from the HBM PHY and coupled with the processor and a memory controller;
• the memory controller coupled with the die-to-die interface and one or more additional memory dies;
• and a memory built-in self-test (MBIST) coupled with the one or more memory dies and the memory controller and configured to
• operate a testing procedure on the one or more memory dies and the memory controller;
• and
• the one or more additional memory dies assembled onto the substrate.

A method comprising:

• initiating, by a memory built-in self-test (MBIST) engine on an interface die of a high- bandwidth memory (HBM) device, one or more first test sequences to test an HBM physical layer (PHY) configured to facilitate communication between a processor and one or more memory dies of the HBM device;
• initiating, by the MBIST engine, one or more second test sequences to test a memory controller and a standard compliant PHY located on the interface die, the memory controller configured to communicate signaling to one or more additional memory dies separate from the HBM device, and the standard compliant PHY configured to facilitate communication between the processor and the memory controller;
• and
• determining an operability of the HBM PHY, the memory controller, and the standard compliant PHY based on the one or more first test sequences and the one or more second test sequences.