Memory device

A memory device, comprising:

• a plurality of first wordlines;
• a plurality of second wordlines;
• a plurality of local bitlines;
• a plurality of complementary local bitlines;
• a plurality of first memory cells connected to the plurality of first wordlines and the plurality of local bitlines;
• a plurality of second memory cells connected to the plurality of second wordlines and the plurality of complementary local bitlines;
• a global bitline;
• a complementary global bitline;
• a plurality of first multiplexers configured to selectively connect each of the plurality of local bitlines to the global bitline or a precharge power line;
• a plurality of second multiplexers configured to selectively connect each of the plurality of complementary local bitlines to the complementary global bitline or the precharge power line;
• a bitline sense amplifier connected to the global bitline and the complementary global bitline;
• and
• a body refresh control circuit configured to:
• control the global bitline and the complementary global bitline to be precharged, and the plurality of local bitlines and the plurality of complementary local bitlines to be connected to the precharge power line, in a first period;
• control at least one complementary target local bitline selected from among the plurality of complementary local bitlines to be connected to the complementary global bitline, in a second period subsequent to the first period;
• control at least one target local bitline selected from among the plurality of local bitlines to be connected to the global bitline, in a third period subsequent the second period;
• and
• control a body refresh operation in which the bitline sense amplifier senses and amplifies a difference in voltage levels between the global bitline and the complementary global bitline in the second period and the third period.

A memory device, comprising:

• a plurality of memory cell blocks, each of the plurality of memory cell blocks comprising a plurality of memory cells connected to a plurality of wordlines and a plurality of local bitlines;
• a plurality of global bitlines, each of the plurality of global bitlines corresponding to two or more local bitlines among the plurality of local bitlines;
• a plurality of multiplexers configured to selectively connect each of the plurality of local bitlines to a corresponding global bitline or a precharge power line;
• a plurality of bitline sense amplifiers, each of the plurality of bitline sense amplifiers connected to two global bitlines among the plurality of global bitlines, and configured to sense and amplify a difference in voltage levels between the two global bitlines;
• and
• a body refresh control circuit configured to control the plurality of multiplexers to connect a plurality of first local bitlines provided in at least one memory cell block among the plurality of memory cell blocks to the precharge power line, and to control perform a body refresh operation comprising lowering a level of the precharge power line.