Hybrid bonding of semiconductor cmos wafer and semiconductor memory array wafer using debondable carriers

A semiconductor device assembly, comprising:

• a first semiconductor wafer having complementary metal-oxide-semiconductor (CMOS) transistor devices, the first semiconductor wafer having a first frontside surface and a first backside surface;
• and
• a second semiconductor wafer having one or more memory arrays, the second semiconductor wafer having a second frontside surface and a second backside surface;
• wherein a bonding interface is formed between the first frontside surface of the first semiconductor wafer and the second frontside surface of the second semiconductor wafer, and
• wherein the first semiconductor wafer having a thickness ranging from 100 nm to 1 μm.

A method of forming a semiconductor device assembly, comprising:

• providing a first carrier wafer having a stacked “dielectric layer-debond layer-dielectric layer” structure on its frontside surface;
• attaching a first semiconductor wafer to the first carrier wafer, the first semiconductor wafer having complementary metal-oxide-semiconductor (CMOS) transistor devices;
• bonding a second semiconductor wafer with the first semiconductor wafer, the second semiconductor wafer being attached on a second carrier wafer and having one or more memory arrays;
• and
• debonding the second carrier wafer from the first semiconductor wafer.