Backside via to power rail via connection

A method of forming a semiconductor structure comprising:

• forming a power rail via between a first and a second transistor, the power rail via including a conductive core surrounded by a core liner, a lower section of the power rail via being surrounded by an inter-level dielectric (ILD) layer, the ILD layer being embedded in a substrate;
• creating an opening in the substrate from a backside of the substrate, the opening extends above a bottom surface of the power rail via to surround a lower portion of the lower section of the power rail via;
• lining the opening with a dielectric liner;
• removing the core liner of the power rail via to expose a bottom surface of the conductive core of the power rail via;
• and
• filling the opening with a conductive material, thereby forming a backside via contacting the conductive core of the power rail via.

A semiconductor structure comprising:

• a first and a second transistor;
• a power rail via between the first and the second transistor, the power rail via including a conductive core and a core liner, the core liner lining the conductive core at a sidewall of the power rail via;
• and
• a backside via below the power rail via and below the first and the second transistor,
• wherein the backside via has a first portion directly contacting the conductive core of the power rail via and a second portion around the first portion, and a top surface of the first portion is above a top surface of the second portion.