US 2026/0011355 A1 · MEMORY DEVICE AND METHOD OF APPLYING AN UNDERDRIVE VOLTAGE

Abstract

A memory device including a memory cell array having memory cells connected to a selected word line, a first voltage regulator configured to generate an underdrive voltage lower than an operating voltage, an address decoder including transistors, and configured to apply, to the selected word line, a voltage received during an underdrive period, a second voltage regulator configured to generate a well voltage to be applied to the transistors, a voltage transfer circuit configured to transfer the underdrive voltage or the well voltage to the address decoder, and a control logic configured, in response to the underdrive voltage being at a negative level, to control the second voltage regulator to set the well voltage to the negative level before the underdrive period, and to control the voltage transfer circuit to transfer the well voltage set to the negative level to the address decoder during the underdrive period.

Claims18

Dependent claims

A memory device comprising:

a memory cell array including memory cells connected to a selected word line;
a first voltage regulator configured to generate an underdrive voltage having a voltage level lower than an operating voltage applied to the selected word line;
an address decoder including a plurality of transistors, and configured to apply, to the selected word line, a voltage received during an underdrive period during which the underdrive voltage is applied to the selected word line;
a second voltage regulator configured to generate a well voltage to be applied to the plurality of transistors;
a voltage transfer circuit configured to transfer the underdrive voltage or the well voltage to the address decoder;
and
a control logic configured, in response to the underdrive voltage being at a negative level, to control the second voltage regulator to set the well voltage to the negative level before the underdrive period, and to control the voltage transfer circuit to transfer the well voltage set to the negative level to the address decoder during the underdrive period.

4 more elements

A method of operating a memory device, comprising:

determining a first underdrive period during which a first underdrive voltage lower than a first operating voltage to be applied to memory cells connected to a selected word line is applied to the selected word line;
in response to the first underdrive voltage to be generated from a first voltage regulator configured to generate the first operating voltage being at a first negative level, generating a first well voltage corresponding to the first underdrive voltage earlier by a first time period than the first underdrive period by a second voltage regulator configured to generate a well voltage to be applied to transistors included in an address decoder;
applying the first well voltage generated from the second voltage regulator to the selected word line during the first underdrive period;
determining a second underdrive period during which a second underdrive voltage lower than a second operating voltage applied to the memory cells is applied to the selected word line;
in response to the second underdrive voltage to be generated from the first voltage regulator being at a second negative level, generating by the second voltage regulator a second well voltage corresponding to the second underdrive voltage earlier by a second time period than the second underdrive period;
and
applying the second well voltage generated from the second voltage regulator to the selected word line during the second underdrive period.

4 more elements

Dependencies are inferred from the claim text.

Memory device and method of applying an underdrive voltage

Life of this patent

Memory device and method of applying an underdrive voltage

Life of this patent

Abstract

Claims18