Chiplet Hub with Private Memory Space Formed from Multiple Memories

A system comprising:

• at least two memories selected from an embedded memory, a die-to-die (D2D) connected memory and a high bandwidth memory (HBM), the HBM having sides and two faces, a first face including connections for providing signals from the HBM;
• at least one computational element selected from an embedded compute unit, a D2D compute chiplet and a D2D accelerator chiplet;
• and
• a chiplet hub, the chiplet hub having two faces and at least three sides, the chiplet hub including:
• a plurality of D2D connection regions on the at least three sides, at least one D2D connection region for connection to a D2D chiplet connected memory when the at least two memories includes a D2D chiplet connected memory and at least one D2D connection region for connection to at least one of a D2D compute chiplet and a D2D accelerator chiplet when the at least one computational element includes at least one of a D2D compute chiplet and a D2D accelerator chiplet;
• an embedded memory when the at least two memories includes an embedded memory;
• an embedded compute unit when the at least one computational element includes an embedded compute unit;
• connections for the signals from the HBM on a first face of the chiplet hub when the at least two memories includes an HBM;
• and
• logic for controlling access to the at least two memories by the at least one computational element, the logic for controlling access to at least two memories includes logic organizing a first portion of memory from each of at least two of the at least two memories as a combined private memory space for exclusive access by one of a first embedded compute unit, a D2D compute chiplet or a D2D accelerator chiplet of the at least one computational element.