Composable infrastructure enabled by heterogeneous architecture, delivered by cxl based cached switch soc and extensible via cxloverethernet (coe) protocols

A system comprising:

• a device comprising:
• a processor;
• a plurality of accelerators configured to accelerate one or more types of workloads;
• a cache coherent switch on chip, communicatively coupled to the plurality of accelerators via a Compute Express Link (CXL) protocol, and configured to bypass the processor to provide cache coherency between the plurality of accelerators using one or more virtual cache hierarchies that include CXL and Peripheral Component Interconnect (PCI) interfaces.

A device comprising:

• a cache coherent switch on chip, communicatively coupled via a Compute Express Link (CXL) protocol to a plurality of accelerators configured to perform a type of workload;
• wherein the cache coherent switch on the chip is configured to bypass a processor of the device to provide cache coherency, between the plurality of accelerators, using one or more virtual cache hierarchies;
• wherein the one or more virtual cache hierarchies are coupled to one or more components;
• and
• wherein the one or more virtual cache hierarchies indicate a priority of a cache for each of the one or more components.

A cache coherent switch on chip comprising:

• a Compute Express Link (CXL) interface communicatively coupled via a Compute Express Link (CXL) protocol to a plurality of accelerators of a device, the plurality of accelerators configured to perform a type of workload;
• wherein the cache coherent switch on the chip is configured to bypass a processor of the device to provide cache coherency between the plurality of accelerators using one or more virtual cache hierarchies;
• wherein one or more virtual cache hierarchies are coupled to one or more components;
• and
• wherein the one or more virtual cache hierarchies indicate a priority of a cache for each of the one or more components.