Extended gate and standard gate integration scheme
AssigneeInternational Business Machines Corporation
InventorsRuqiang Bao, Anthony I-Chih Chou, Tushar Gupta
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Abstract
Embodiments of the invention include a semiconductor structure having a first transistor including first channel regions, a high-k dielectric layer on the first channel regions, and gate material on the high-k dielectric layer. A second transistor includes second channel regions, a nitride layer on the second channel regions, the high-k dielectric layer on the nitride layer, and the gate material on the high-k dielectric layer. The first and second channel regions include a corresponding number of semiconductor layers.
Claims20
A semiconductor structure comprising:
- a first transistor comprising first channel regions, a high-k dielectric layer on the first channel regions, and gate material on the high-k dielectric layer;
- and
- a second transistor comprising second channel regions, a nitride layer on the second channel regions, the high-k dielectric layer on the nitride layer, and the gate material on the high-k dielectric layer, wherein the first and second channel regions comprise a corresponding number of semiconductor layers.
A method comprising:
- providing a first transistor comprising first channel regions, a high-k dielectric layer on the first channel regions, and gate material on the high-k dielectric layer;
- and
- providing a second transistor comprising second channel regions, a nitride layer on the second channel regions, the high-k dielectric layer on the nitride layer, and the gate material on the high-k dielectric layer, wherein the first and second channel regions comprise a corresponding number of semiconductor layers.
A method comprising:
- forming an oxide layer above first channel regions of a first transistor and on second channel regions of a second transistor;
- converting the oxide layer to a nitride layer;
- removing the nitride layer above the first channel regions of the first transistor, while the nitride layer remains on the second channel regions of the second transistor;
- forming a high-k dielectric layer on the first channel regions of the first transistor and on the nitride layer on the second channel regions of the second transistor;
- and
- forming gate material on the high-k dielectric layer of the first transistor and the second transistor, wherein the first and second channel regions comprise a corresponding number of semiconductor layers.
Dependencies are inferred from the claim text.