Memory cell

A memory cell comprising a doped well of a first conductivity type and a transistor, the transistor comprising:

• a doped first region of a second conductivity type opposite to the first conductivity type, the first doped region disposed in the doped well;
• a buried doped channel of the second conductivity type extending in the doped well;
• and
• a gate stack overlying the doped well above the buried doped channel, the gate stack comprising a first layer adapted to trap charges, a second insulating layer overlying the first layer, and a third conductive layer resting on the second layer.

A method for controlling a memory cell that comprises an n-type doped first region disposed in a p-type doped well, an n-type doped buried channel extending into the doped well, and a gate stack overlying the doped well above the buried doped channel and comprising a first layer, a second insulating layer overlying the first layer, and a third conductive layer resting on the second layer, the method comprising:

• applying a first potential to the first region, wherein the first potential is in the range from 3 V to 7 V;
• applying a reference potential to the doped well;
• and
• applying a third potential to the third conductive layer of the gate stack, wherein the third potential is in the range from −6 V to −12 V.