Analog-to-digital converter with gray counter

An analog-to-digital converter (ADC), comprising:

• a plurality of ADC circuits, each ADC circuit being associated to a pixel group of an pixel array and comprising a storage circuit comprising a plurality of storage cells;
• a shared counter circuit having a counter control connection to apply a clock signal and a plurality of counter output connections, the shared counter circuit being configured to generate a respective counter bit in response to a counter state of the counter circuit, wherein a respective one of the storage cells is connected to a respective one of the counter output connections for storing the respective counter bit, wherein the shared counter circuit comprises a Gray ripple counter;
• and
• a delay circuit connected to one or more storage cells of the plurality of storage cells and configured to delay a write control signal for storing a counter bit into a storage cell of the one or more storage cells, wherein the delay for the write control signal increases from lower counter bits to higher counter bits to account for a ripple delay introduced by the Gray ripple counter.

An image sensor, comprising:

• a pixel array including at least two pixel groups, each pixel group comprising a plurality of pixels connected to a respectively associated group bus of that pixel group;
• and
• an analog-to-digital converter (ADC), the ADC comprising:
• a plurality of ADC circuits, each ADC circuit being associated to a pixel group of a pixel array and comprising a storage circuit comprising a plurality of storage cells;
• a shared counter circuit having a counter control connection to apply a clock signal and a plurality of counter output connections, the shared counter circuit being configured to generate a respective counter bit in response to a counter state of the counter circuit, wherein a respective one of the storage cells is connected to a respective one of the counter output connections for storing the respective counter bit, wherein the shared counter circuit comprises a Gray ripple counter;
• and
• a delay circuit connected to one or more storage cells of the plurality of storage cells and configured to delay a write control signal for storing a counter bit into a storage cell of the one or more storage cells, wherein the delay for the write control signal increases from lower counter bits to higher counter bits to account for a ripple delay introduced by the Gray ripple counter.