Package architectures having vertically stacked dies with direct bonding

Abstract

Embodiments of a microelectronic assembly may include a first integrated circuit (IC) die having a first surface, an opposing second surface, and a third surface orthogonal to the first and second surfaces, the first IC die including conductive traces parallel to the first and second surfaces and exposed at the third surface; and a second IC die having a fourth surface with conductive contacts, wherein the conductive traces exposed at the third surface of the first IC die are electrically coupled to the conductive contacts at the fourth surface of the second IC die by metal-metal bonds including nanotwinned copper and dielectric-dielectric bonds. In some embodiments, the first IC die may be one of a plurality of first IC dies. In such embodiments, some of the plurality of first IC dies may include memory circuitry and some of the plurality of first IC dies may include compute circuitry.

Dependencies are inferred from the claim text.