US 2025/0384902 A1 · SEMICONDUCTOR STRUCTURE AND PREPARATION METHOD THEREOF

Abstract

A semiconductor structure and a preparation method thereof are provided. The semiconductor structure includes: a substrate; a plurality of memory cells arranged in a first direction and a second direction, each of the memory cells including a first transistor, a first memristor, a second transistor, and a second memristor; where the first and second directions are parallel to a plane of the substrate and intersect; and a plurality of first and second bit lines extending in the first direction. In every two adjacent rows of memory cells arranged in the first direction, all the first memristors in a first row and all the second memristors in a second row are connected to a same first bit line, and all the second memristors in the first row and all the first memristors in the second row are connected to a same second bit line.

Claims10

Dependent claims

A semiconductor structure, comprising:

a substrate;
a plurality of memory cells arranged in a first direction and a second direction;
wherein each of the plurality of memory cells comprises a first transistor, a first memristor connected to the first transistor, a second transistor, and a second memristor connected to the second transistor;
wherein the first direction and the second direction are parallel to a plane of the substrate and intersect;
and
a plurality of first bit lines extending in the first direction and a plurality of second bit lines extending in the first direction;
wherein in every two adjacent rows of memory cells arranged in the first direction, the first memristors in a first row and the second memristors in a second row are connected to a same first bit line, and the second memristors in the first row and the first memristors in the second row are connected to a same second bit line.

4 more elements

A method for preparing a semiconductor structure, comprising:

providing a substrate;
forming a plurality of memory cells arranged in a first direction and a second direction, each of the plurality of memory cells comprising a first transistor, a first memristor connected to the first transistor, a second transistor, and a second memristor connected to the second transistor;
wherein the first direction and the second direction are parallel to a plane of the substrate and intersect;
and
forming a plurality of first bit lines extending in the first direction and a plurality of second bit lines extending in the first direction;
wherein in every two adjacent rows of memory cells arranged in the first direction, the first memristors in a first row and the second memristors in a second row are connected to a same first bit line, and the second memristors in the first row and the first memristors in the second row are connected to a same second bit line.

3 more elements

Dependencies are inferred from the claim text.

Semiconductor structure and preparation method thereof

Life of this patent

Semiconductor structure and preparation method thereof

Life of this patent

Abstract

Claims10