US 2025/0384259 A1 · ANALOG PULSE FREQUENCY NEURAL NETWORK ASIC

Abstract

An analog or mixed-signal ASIC implements and trains a neural-network model entirely in the analog domain. Weights and activations are encoded as pulse frequencies. Forward propagation is performed by analog multipliers, while reverse-propagation error signals are conveyed through reverse directional nodes and error neurons that inject pulse-based corrections upstream, eliminating digital gradient arithmetic. Variable analog weight-storage elements—including field-effect transistors, switched-capacitor arrays, and phase-change memory—are updated in real time. Additional features include flash-ADC calibration with temperature compensation, auto-associative pattern completion, stochastic-computing variants, dynamic gate-array reconfiguration, and optional wireless telemetry. Continuous on-edge learning is achieved at ultra-low power for sensor-rich edge-AI applications.

Claims20

Dependent claims

A method of operating an analog neural-network applications-specific integrated circuit (ASIC), the method comprising:

(a) representing each synaptic weight and neuron activation as a frequency of electrical pulses;
(b) generating forward-propagation signals by modulating said pulse frequencies through analog multiplication stages;
(c) generating reverse-propagation error signals via reverse directional nodes that propagate error pulses backward through the network without executing conventional digital back-propagation arithmetic;
(d) adjusting each synaptic weight in real time by directly modifying a corresponding analog parameter selected from the group consisting of voltage, capacitance, conductance, current, or resistance based on at least one of amplitude, frequency, or duty-cycle of the received error pulses;
and
(e) continually updating network parameters on-edge to support on-the-fly learning with reduced energy consumption compared with digital implementations.

3 more elements

An analog neural-network ASIC comprising:

(a) a plurality of islanded computational modules;
(b) a pulse-frequency encoder that converts analog or digital external input data—including values originating from physical sensors, digitized sensor streams, or purely computational sources—into corresponding analog pulse trains;
(c) an analog multiplier array within each module that multiplies incoming pulse-frequency signals by local analog weights;
(d) reverse directional nodes coupled to the multiplier array and configured to propagate error-representative pulse trains upstream without digital computation of weight corrections;
(e) a weight-adjustment circuit including analog storage elements selected from variable resistors, variable capacitors, field-effect transistors, or phase-change memory cells, each element being updated in real time by the frequency or duty-cycle of the associated error pulses;
(f) an interconnect network that couples the islanded computational modules such that pulse-frequency signals propagate between modules;
and
(g) a pulse-frequency decoder that converts final network outputs to digital form;
wherein the ASIC performs inference and on-chip training without employing a regular row-and-column cross-bar array and without any digital processor that calculates per-synapse change in weight values.

6 more elements

Dependencies are inferred from the claim text.

Analog pulse frequency neural network asic

Life of this patent

Analog pulse frequency neural network asic

Life of this patent

Abstract

Claims20