Host accelerated operations in managed nand devices
AssigneeLodestar Licensing Group LLC
InventorsSebastien Andre Jean, Greg A. Blodgett
Life of this patent
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Abstract
Devices and techniques for host accelerated operations in managed NAND devices are described herein. A host logical-to-physical (L2P) table of the NAND device has an associated map. Entries in the map correspond to one or more logical addresses (LA) and indicate whether the host L2P table is current for those LAs. If the table is not current, then a request will bypass the host L2P table, using a standard device L2P lookup instead. Otherwise, the host L2P table can be used.
Claims20
A memory device comprising:
- a memory array;
- and
- a controller coupled to the memory array and configured to couple to a host, wherein the controller is configured to:
- receive a memory access request comprising a host logical-to-physical (L2P) entry of a host L2P table stored in the host;
- determine that the host L2P entry is invalid based on a comparison of a token included in the memory access request with a verification component stored in the memory array, wherein the verification component corresponds to a physical address included in the host L2P entry;
- and
- notify the host to refresh the host L2P table in response to a number of invalid host L2P entries exceeding a threshold.
An electronic system comprising:
- a host comprising a host logical-to-physical (L2P) table stored therein;
- a memory array;
- and
- a controller coupled to the memory array and configured to couple to the host, wherein the controller is configured to:
- receive a memory access request comprising a host L2P entry of the host L2P table;
- determine that the host L2P entry is invalid based on a comparison of a token included in the memory access request with a verification component stored in the memory array, wherein the verification component corresponds to a physical address included in the host L2P entry;
- and
- notify the host to refresh the host L2P table in response to a number of invalid host L2P entries exceeding a threshold.
Tangible, non-transitory, computer-readable media storing instructions that, when executed by processing circuitry, cause the processing circuitry to:
- receive a memory access request for accessing a memory array, wherein the memory access request comprises a host logical-to-physical (L2P) entry of a host L2P table stored in a host;
- determine that the host L2P entry is invalid based on a comparison of a token included in the memory access request with a verification component stored in the memory array, wherein the verification component corresponds to a physical address included in the host L2P entry;
- and
- notify the host to refresh the host L2P table in response to a number of invalid host L2P entries exceeding a threshold.
Dependencies are inferred from the claim text.