US 2025/0377973 A2 · DATA ROUTING FOR ERROR CORRECTION IN STACKED MEMORY ARCHITECTURES

Abstract

Methods, systems, and devices for data routing for error correction in stacked memory architectures are described. A system may support error correction of bits of data communicated between a first semiconductor die (e.g., an array die) and a second semiconductor die (e.g., a logic die). For example, an interface of the second semiconductor die may receive data stored at a memory array of the first semiconductor die. The interface may include error correction engines each operable to correct one or more bit errors. The interface may also include logic circuitry operable to route physically-grouped subsets of the received data to respective error correction engines, and such subsets may be configured to allocate the error correction engines in manner that improves a likelihood that physically-grouped errors in the system can be corrected. The interface may output the data to a host system after the error control operations are performed.

Claims30

Dependent claims

A system, comprising:

one or more first semiconductor dies comprising:
one or more memory arrays;
and
one or more first interfaces each comprising first circuitry operable to access at least one corresponding memory array of the one or more memory arrays;
and
a second semiconductor die coupled with the one or more first semiconductor dies, the second semiconductor die comprising:
one or more second interfaces, each second interface comprising:
a plurality of error correction engines each operable to correct one or more bit errors;
second circuitry operable to receive data, from a respective first interface, stored at a corresponding memory array;
and
logic circuitry operable to route a first subset of the received data to a first error correction engine of the plurality of error correction engines and a second subset of the received data to a second error correction engine of the plurality of error correction engines.

8 more elements

Dependencies are inferred from the claim text.

Data routing for error correction in stacked memory architectures

Life of this patent

Data routing for error correction in stacked memory architectures

Life of this patent

Abstract

Claims30