Semiconductor processing integration for bipolar junction transistor (bjt)

A method, comprising:

• forming a gate layer over a semiconductor substrate in a bipolar junction transistor (BJT) region and a complementary field effect transistor (CFET) region;
• patterning the gate layer into a gate electrode of a field effect transistor (FET) in the CFET region;
• forming a first etch stop layer conformally over the semiconductor substrate in the BJT region and the CFET region and over the gate electrode;
• forming a collector layer on the semiconductor substrate and in an opening through the first etch stop layer in the BJT region;
• forming a base layer on the collector layer and at least partially over the first etch stop layer;
• and
• forming an emitter layer on the base layer.

A method, comprising:

• forming a gate layer over a semiconductor substrate in a bipolar junction transistor (BJT) region and a complementary field effect transistor (CFET) region;
• patterning the gate layer in the CFET region into a gate electrode of a field effect transistor (FET) in the CFET region;
• forming a first etch stop layer conformally in the CFET region and the BJT region, the first etch stop layer being along a side of the gate electrode and over the gate electrode;
• forming a collector layer on the semiconductor substrate and through an opening in the first etch stop layer in the BJT region;
• forming a material of a base layer over the collector layer and over the first etch stop layer;
• forming a material of an emitter layer over the base layer;
• patterning the material of the emitter layer into the emitter layer in the BJT region;
• and
• patterning the material of the base layer into the base layer in the BJT region.