Read offset compensation in read operation of memory device
AssigneeYangtze Memory Technologies Co., Ltd.
InventorHua TAN
Life of this patent
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AssigneeYangtze Memory Technologies Co., Ltd.
InventorHua TAN
Estimating the term…
A memory controller coupled to a memory device including an array of memory cells, each memory cell being set to one of 2N states corresponding to a piece of N-bits data, where N is an integer greater than 1, and the array of memory cells being partitioned into one or more units. The memory controller is coupled to the memory device and configured to, upon executing instructions, obtain, from the memory device, a number P of memory cells in a unit of the units that are in one or more programmed states of the 2N states; calculate, based on the number P, a compensated read voltage with an offset from a default read voltage; and provide, to the memory device, the compensated read voltage for a read operation performed on a selected memory cell of the memory cells in a unit of the units.
A memory system, comprising:
A method of reading a memory device comprising an array of memory cells being partitioned into one or more units, each memory cell of one unit being configured to store N-bit data and be set to one of 2N states corresponding to the N-bit data, and N is an integer greater than 1, the method comprising:
A storage medium comprising an instruction stored therein, wherein the instruction, when running, controls a memory system to perform a method of reading a memory device of the memory system, the memory device comprising an array of memory cells being partitioned into one or more units, each memory cell of one unit being configured to store N-bit data and be set to one of 2N states corresponding to the N-bit data, and N being an integer greater than 1;
Dependencies are inferred from the claim text.