Memory, operation method of memory, and memory system

A memory, comprising a memory array and a peripheral circuit coupled to the memory array, wherein:

• the peripheral circuit comprises a control logic circuit and a page buffer;
• the page buffer is coupled with the memory array through a bit line;
• the control logic circuit is coupled with the page buffer through a signal line;
• the page buffer comprises a first page buffer and a second page buffer;
• the control logic circuit is coupled with the first page buffer through a first stagger control line and is coupled with the second page buffer through a second stagger control line;
• and
• the control logic circuit is configured to:
• apply an operation voltage to the page buffer through the signal line;
• and
• during the application of the operation voltage to the page buffer, apply a control voltage to the first page buffer through the first stagger control line in a first stage and apply the control voltage to the second page buffer through the second stagger control line in a second stage, so as to control the first page buffer and the second page buffer to work in a stagger manner.