US 2025/0372154 A1Published application

Semiconductor device having input buffer circuit

AssigneeMicron Technology, Inc.

InventorsShun Nishimura, Hiroyuki Matsuno

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Abstract

An example apparatus includes: first and second inverters cross-coupled to each other, a first transistor coupled between the first and third circuit nodes; a second transistor coupled between the second and fourth circuit nodes; a plurality of third transistors coupled in parallel between the third circuit node and the second power line; and a plurality of fourth transistors coupled in parallel between the fourth circuit node and the second power line. When the control code signal indicates a first value: at least one of the plurality of third transistors is brought into an OFF state; remaining one or ones of the plurality of third transistors are brought into an ON state; at least one of the plurality of fourth transistors is brought into an OFF state; and remaining one or ones of the plurality of fourth transistors are brought into an ON state.

Claims20

Dependent claims

An apparatus comprising:

first and second input nodes;
first and second power lines supplied with first and second power potentials different from each other;
a first current path including a first transistor and a first source control circuit coupled in series between the first and second power lines, the first transistor being configured to be controlled responsively to a first signal at the first input node and the first source control circuit having a plurality of second transistors coupled in parallel;
and
a second current path including a third transistor and a second source control circuit coupled in series between the first and second power lines, the third transistor being configured to be controlled responsively to a second signal at the second input node and the second source control circuit having a plurality of fourth transistors coupled in parallel;
wherein each of the plurality of second and fourth transistors is configured to be controlled by a control code signal, and
wherein, when the control code signal indicates a first value:
at least one of the plurality of second transistors is brought into an OFF state;
remaining one or ones of the plurality of second transistors are brought into an ON state;
at least one of the plurality of fourth transistors is brought into an OFF state;
and
remaining one or ones of the plurality of fourth transistors are brought into an ON state.

9 more elements

An apparatus comprising:

a first power line supplied with a first power potential;
a second power line supplied with a second power potential different from the first power potential;
a flip-flop circuit coupled to the first power line and having first and second input nodes and first and second output nodes;
a first transistor and a first current control circuit coupled in series between the first input node of the flip-flop circuit and the second power line;
a second transistor and a second current control circuit coupled in series between the second input node of the flip-flop circuit and the second power line;
a third transistor coupled between the first power line and a common source line;
a fourth transistor coupled between the common source line and a control electrode of the first transistor, the fourth transistor having a control electrode supplied with an input signal from outside;
and
a fifth transistor coupled between the common source line and a control electrode of the second transistor, the fifth transistor having a control electrode supplied with a reference potential,
wherein each of the first and second current control circuits is configured to be controlled in a driving ability by a control code signal, and
wherein, when the control code is incremented from a first value to a second value, the driving ability of both the first and second current control circuits changes.

8 more elements

An apparatus comprising:

a first power line supplied with a first power potential;
a second power line supplied with a second power potential different from the first power potential;
a flip-flop circuit coupled to the first power line and having first and second input nodes and first and second output nodes;
a first transistor and a first current control circuit coupled in series between the first input node of the latch circuit and the second power line;
a second transistor and a second current control circuit coupled in series between the second input node of the latch circuit and the second power line;
a third transistor coupled between the first power line and a common source line;
a fourth transistor coupled between the common source line and a control electrode of the first transistor, the fourth transistor having a control electrode supplied with an input signal from outside;
a fifth transistor coupled between the common source line and a control electrode of the second transistor, the fifth transistor having a control electrode supplied with a reference potential;
and
a decoder circuit configured to generate a first code signal and a second control signal based on a control code signal,
wherein the first current control circuit is configured to be controlled in a driving ability by the first control code,
wherein the second current control circuit is configured to be controlled in a driving ability by the second control code, and
wherein the decoder circuit is configured to:
change the first code signal based on the control code signal without changing the second code signal when a value of the control code signal is within a first range;
change the second code signal based on the control code signal without changing the first code signal when a value of the control code signal is within a second range;
and
change both the first and second control code signals based on the control code signal when a value of the control code signal is within a third range.

14 more elements

Dependencies are inferred from the claim text.