Data-valid window tracking for high speed interface
AssigneeSanDisk Technologies LLC
InventorsShiv Mathur, Sajal Mittal, Jayanth Thimmaiah
Life of this patent
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Abstract
An apparatus includes one or more control circuit configured to connect to a data bus. The one or more control circuit is configured to compare a first bit sampled on a first side of a Data Valid Window (DVW) of a data signal with a middle bit from the middle of the DVW and compare a second bit sampled on a second side of the DVW with the middle bit to detect misalignment of sampling with the DVW. The one or more control circuit is configured to adjust sampling times for the data signal according to detection of misalignment.
Claims20
An apparatus, comprising:
- one or more control circuit configured to connect to a data bus, the one or more control circuit configured to:
- compare a first bit sampled on a first side of a Data Voltage Window (DVW) of a data signal with a middle bit from the middle of the DVW to detect first misalignment of sampling with the DVW, compare a second bit sampled on a second side of the DVW with the middle bit to detect second misalignment of sampling with the DVW and adjust sampling times for the data signal according to detection of the first or second misalignment.
A method of Data Valid Window (DVW) tracking, the method comprising:
- receiving a data signal;
- sampling the data signal at a first time on a first side of a DVW to obtain a first bit;
- sampling the data signal at a second time on a second side of the DVW to obtain a second bit;
- sampling the data signal at a third time between the first time and the second time to obtain a middle bit;
- comparing the first bit and the middle bit to detect first misalignment of sampling with the DVW;
- comparing the second bit and the middle bit to detect second misalignment of sampling with the DVW;
- and
- in response to detecting first DVW misalignment or second DVW misalignment, adjusting timing of sampling the data signal.
A system comprising:
- a memory controller die;
- one or more nonvolatile memory dies;
- a data bus connecting the memory controller die to the one or more nonvolatile memory dies, the data bus configured to convey data signals between the memory controller die and the one or more nonvolatile memory dies;
- and
- means for comparing a first bit sampled on a first side of a DVW of a data signal of the data bus with a middle bit from the middle of the DVW to detect first misalignment of sampling with the DVW, comparing a second bit sampled on a second side of the DVW with the middle bit to detect second misalignment of sampling with the DVW and adjusting sampling times for the data signal according to detection of the first or second misalignment.
Dependencies are inferred from the claim text.