Exposing valid byte lanes as vector predicates to cpu

A device comprising:

• a functional unit;
• a memory controller coupled to the functional unit by a data path having a data path size, wherein the memory controller comprises:
• a first register having a size defined by a first plurality of bits equal to the data path size;
• and
• a second register having a size defined by a second plurality of bits, each bit of the second plurality of bits corresponding to a respective subset of the first plurality of bits;
• wherein the memory controller is configured to:
• cause a first vector of a data stream to be stored into the first register, the first vector having one or more data elements;
• responsive to a size of the first vector being less than the size of the first register, storing a fixed value in locations of the first register in which the first vector is not stored;
• and
• storing in each bit of the second register, a first state responsive to the corresponding respective subset of the first plurality of bits containing a data element of the vector stream and a second state responsive to the corresponding respective subset of the first plurality of bits containing the fixed value.