Semiconductor device having wide tuning range varactor and method of manufacturing the same

A semiconductor device comprising:

• fin structures on a substrate, the fin structures extending in a first direction;
• a first gate structure on the fin structures, the first gate structure extending in a second direction perpendicular to the first direction;
• a second gate structure on the fin structures, the second gate structure extending in the second direction and being spaced apart from the first gate structure in the first direction;
• first and second source/drain (S/D) electrodes on the fin structures, wherein:
• the first and second gate structures are between the first and second S/D electrodes;
• a third S/D electrode on the fin structures, wherein:
• the third S/D electrode is between the first and second gate structures;
• epitaxy structures between the first, second, and third S/D electrodes and the fin structures, and electrically connecting the first, second, and third S/D electrodes with the fin structures;
• a first interconnection structure electrically connected to each of the first and second gate structures;
• and
• a second interconnection structure electrically connected to the first and second S/D electrodes, and being free of a connection to the third S/D electrode.

A semiconductor device comprising:

• fin structures extending in a first direction;
• a first gate structure extending in a second direction, perpendicular to the first direction, and crossing the fin structures;
• a second gate structure extending in the second direction, crossing the fin structures, and spaced apart from the first gate structure in the first direction;
• first and second source/drain (S/D) electrodes on the fin structures, wherein:
• the first and second gate structures are between the first and second S/D electrodes;
• a third S/D electrode on the fin structures, wherein:
• the third S/D electrode is between the first and second gate structures;
• epitaxy structures between the first, second, and third S/D electrodes and the fin structures, and electrically connecting the first, second, and third S/D electrodes with the fin structures;
• a buffer structure contacting each of the first and second gate structures;
• at least one terminal on the buffer structure;
• a first interconnection structure electrically connected to the first and second gate structures, wherein:
• the first interconnection structure is electrically connected to the first and second gate structures through the at least one terminal and the buffer structure;
• and
• a second interconnection structure electrically connected to the first and second S/D electrodes, and being free of a connection to the third S/D electrode.