Dynamic, random-access memory with interleaved refresh

A memory device comprising:

• an array of memory cells, the array of memory cells including columns of memory cells each selectively coupled to a bitline;
• an access sense amplifier coupled to the bitline;
• a refresh sense amplifier coupled to the bitline;
• and
• a control circuitry coupled to the access sense amplifier and the refresh sense amplifier, the control circuitry to:
• control the refresh sense amplifier to connect to the bitline, sense a voltage on the bitline, amplify the sensed voltage into a bit voltage, store the bit voltage, and disconnect from the bitline;
• control the refresh sense amplifier to reconnect to the bitline to charge the bitline toward a refresh voltage to refresh a memory cell;
• and
• before the bitline charges to the refresh voltage;
• disconnect the refresh sense amplifier from the bitline without having refreshed the memory cell;
• and
• control the access sense amplifier to connect to the bitline.

A method for accessing and refreshing memory cells in a dynamic, random-access memory (DRAM), the memory cells selectively connected to a bitline, the method comprising:

• receiving successive first and second access requests directed to the bitline;
• performing successive first and second access transactions responsive to the respective first and second access requests, each access transaction including an access set-up period and an access sense period;
• generating a refresh request asynchronous with respect to the first and second access requests and directed to the bitline during the first access transaction and, responsive to the refresh request:
• interpreting the refresh request over a refresh set-up period during the first access transaction;
• and
• sensing a voltage on the bitline over a refresh sense period during the set-up period of the second access transaction.