US 2025/0336718 A1 · LOW-K INTERCONNECT DIELECTRIC BY SELECTIVE IMPLANTATION

Abstract

A multi-level interconnect structure is formed on a semiconductor wafer to include conductive interconnect structures formed over an interconnect region and capacitor-terminal structures formed over a capacitor region by selectively implanting one or more inter-layer dielectric (ILD) layers over the interconnect region with a capacitance-reducing implant species while protecting each ILD layer over the capacitor region from the capacitance-reducing implant species, thereby forming a relatively lower-capacitance interconnect structure over the interconnect region and a relatively higher-capacitance capacitor over the capacitor region.

Claims20

Dependent claims

A method for fabricating integrated-circuit (IC) devices, comprising:

providing a semiconductor wafer containing a plurality of IC devices;
and
forming an interconnect structure over the plurality of IC devices on the semiconductor wafer which comprises a plurality of conductive interconnect structures formed over an first region and a plurality of capacitor-terminal structures formed over a second region by selectively implanting a dielectric constant-changing implant species into one or more inter-layer dielectric (ILD) layers located over the first region, but not into the one or more ILD layers located over the second region, so that the one or more ILD layers located over the first region have a different dielectric constant than the one or more layers located over the second region.

An integrated-circuit (IC) device comprising:

a semiconductor substrate comprising one or more IC components;
and
a multi-level interconnect structure formed on the semiconductor substrate, the multi-level interconnect structure comprising:
a plurality of first metal structures formed in a first plurality of inter-layer dielectric (ILD) layers and electrically coupled to at least some of the one or more IC components, and
a plurality of second metal structures formed in a second plurality of ILD layers and electrically coupled to at least some of the one or more IC components;
where the first plurality of ILD layers comprises a first concentration of dielectric constant-changing implant species and has a first dielectric constant value, and where the second plurality of ILD layers comprises a second concentration of dielectric constant-changing implant species and has a second dielectric constant value which is different from the first dielectric constant value.

3 more elements

A method, comprising:

forming a plurality of integrated-circuit (IC) devices on a semiconductor substrate;
forming a dielectric layer over the semiconductor substrate to cover the plurality of IC devices;
selectively implanting a capacitance-reducing implant species into a first region of the dielectric layer while protecting a second region of the dielectric layer from implantation by the capacitance-reducing implant species, thereby forming the first region of the dielectric layer with a first dielectric constant value and the second region of the dielectric layer with a second dielectric constant value that is larger than the first dielectric constant value;
and
forming one or more conductive structures in the first and second regions of the dielectric layer.

2 more elements

Dependencies are inferred from the claim text.

Low-k interconnect dielectric by selective implantation

Life of this patent

Low-k interconnect dielectric by selective implantation

Life of this patent

Abstract

Claims20