Apparatus and method for processing receive data in a receive data path including parallel fec decoding

A method comprising:

• at a receiver PHY,
• receiving, in a receive data path, an input data stream having an input bit width;
• converting the input data stream having the input bit width to a first output data stream having a first output bit width and to a second output data stream having a second output bit width;
• performing, at least partially in parallel with the receive data path, a forward error correction (FEC) decoding process on one or more FEC code words of the second output data stream having the second output bit width to produce one or more error correction values;
• and
• correcting one or more symbols, one or more partial symbols, or both, in the first output data stream having the first output bit width at least partially based on the one or more error correction values.

An apparatus comprising:

• a receiver PHY including:
• a data width converter, the data width converter in a receive data path, the data width converter including an input to receive an input data stream having an input bit width, a first output to produce a first output data stream having a first output bit width, and a second output to produce a second output data stream having a second output bit width;
• a forward error correction (FEC) decoder, at least a portion of the FEC decoder in parallel with the receive data path, the FEC decoder including an input to receive the second output data stream having the second output bit width, the FEC decoder including an error correction output to produce one or more error correction values at least partially based on one or more FEC code words in the second output data stream, the one or more error correction values for correction of one or more symbols, one or more partial symbols, or both, in the first output data stream having the first output bit width;
• and
• an error locator of the FEC decoder, the error locator in parallel with the receive data path, the error locator including an error locator polynomial (ELP) algorithm,
• wherein processes in the receive data path execute at a first clock rate of a first clock signal, and
• wherein the error locator executes at a second clock rate of a second clock signal, the second clock rate greater than the first clock rate.