Semiconductor device and methods of formation

A stacked semiconductor device, comprising:

• a first semiconductor die, comprising:
• a first backend dielectric layer;
• a first bonding dielectric layer above the first backend dielectric layer;
• a first metallization layer, in the first backend dielectric layer, comprising:
• a first top conductive structure having a first width,
• wherein an entirety of a first top surface of the first top conductive structure is in physical contact with the first backend dielectric layer;
• and
• a second top conductive structure having a second width that is greater than the first width;
• a first bonding via in physical contact with a second top surface of the second top conductive structure;
• and
• a first bonding pad in physical contact with the bonding via;
• and
• a second semiconductor die, bonded with the first semiconductor die such that the first semiconductor die and the second semiconductor die are vertically arranged in the stacked semiconductor device, comprising:
• a second backend dielectric layer;
• a second bonding dielectric layer below the second backend dielectric layer;
• a second metallization layer, in the second backend dielectric layer, comprising a third top conductive structure;
• a second bonding via in physical contact with a third top surface of the third top conductive structure;
• and
• a second bonding pad in physical contact with the second bonding via,
• wherein the first bonding pad of the first semiconductor die and the second bonding pad of the second semiconductor die are bonded in a metal-to-metal bond, and
• wherein the first bonding dielectric layer of the first semiconductor die and the second bonding dielectric layer of the second semiconductor die are bonded in a dielectric-to-dielectric bond.

A method, comprising:

• forming a first recess and a second recess in a first dielectric layer above a substrate of a semiconductor die;
• forming a patterned masking layer above the first dielectric layer such that the first recess and the second recess are exposed through the patterned masking layer,
• wherein a first width of a first opening in the patterned masking layer above the first recess is less than a second width of a second opening in the patterned masking layer above the second recess;
• forming, through the first opening in the patterned masking layer, a first top interconnect structure in the first recess and a first top conductive structure on the first top interconnect structure;
• forming, through the second opening in the patterned masking layer, a second top interconnect structure in the second recess and a second top conductive structure on the second top interconnect structure;
• forming a second dielectric layer on the first dielectric layer such that the second dielectric layer encapsulates the first top conductive structure and the second top conductive structure;
• forming a third recess through the second dielectric layer to the second top conductive structure;
• forming, while the first top conductive structure remains encapsulated by the second dielectric layer, a bonding via on the second top conductive structure in the third recess in the second dielectric layer;
• and
• forming, while the first top conductive structure remains encapsulated by the second dielectric layer, a bonding pad on the bonding via.