Prescaler with differential clock inputs for high frequency operation
AssigneeQUALCOMM Incorporated
InventorsSang Wook PARK, Junheng ZHU
Life of this patent
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Abstract
Aspects relate to a divide by 3 prescaler for an integrated circuit. An apparatus includes a first logic block configured to generate a first input pulse at a rising edge of a clock signal, and a second logic block configured to generate a second input pulse after the first input pulse that ends at a falling edge of the clock signal. The falling edge is for a clock cycle subsequent to the rising edge. A third logic block is coupled to the first input pulse and the second input pulse and configured to generate a divide by 3 clock output.
Claims20
A divide by 3 prescaler for an integrated circuit, the divide by 3 prescaler comprising:
- a first logic block configured to generate a first input pulse at a rising edge of a clock signal;
- a second logic block configured to generate a second input pulse after the first input pulse that ends at a falling edge of the clock signal, the falling edge being for a clock cycle subsequent to the rising edge;
- and
- a third logic block coupled to the first input pulse and the second input pulse and configured to generate a divide by 3 clock output.
A method of operating a divide by 3 prescaler, the method comprising:
- generating a first input pulse at a rising edge of a clock signal at a first logic block;
- generating a second input pulse at a second logic block, the second input pulse being after the first input pulse and ending at a falling edge of the clock signal, the falling edge being for a clock cycle subsequent to the rising edge;
- and
- generating a divide by 3 clock output at a third logic block in response to the first input pulse and the second input pulse.
A divide by 3 prescaler for an integrated circuit, the divide by 3 prescaler comprising:
- a first logic block configured to generate a first input pulse in response to a clock signal;
- a second logic block configured to generate a second input pulse delayed after the first input pulse by a half cycle of the clock signal;
- and
- a third logic block coupled to the first input pulse and the second input pulse and configured to odd divide the clock signal in response to the first input pulse and the second input pulse to generate a divide by 3 clock output.
Dependencies are inferred from the claim text.