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US 2025/0285809 A1Published application
Structure and methods of forming the structure
AssigneeLodestar Licensing Group LLC
InventorTae Heui Kwong
Life of this patent
Estimating the term…
Abstract
Capacitors, apparatus including a capacitor, and methods for forming a capacitor are provided. One such capacitor may include a first conductor a second conductor above the first conductor, and a dielectric between the first conductor and the second conductor. The dielectric does not cover a portion of the first conductor; and the second conductor does not cover the portion of the first conductor not covered by the dielectric.
Claims20
A memory device, comprising:
- a stack structure including tiers vertically stacked relative to one another and respectively comprising conductive material vertically neighboring dielectric material, the stack structure having at least one stair step structure individually including steps defined by horizontal ends of at least some of the tiers;
- pillars respectively comprising semiconductor material vertically extending completely through the stack structure;
- and
- conductive contacts within a horizontal area of the at least one stair step structure of the stack structure, the conductive contacts individually in physical contact with the conductive material of a respective tier of the stack structure at a respective step of the at least one stair step structure.
1 more element
A non-volatile memory device, comprising:
- a stack structure including conductive structures vertically alternating with dielectric structures, the stack structure comprising:
- a memory array region including vertically extending strings of non-volatile memory cells within a horizontal area thereof;
- and
- a stair step region horizontally offset from the memory array region in a first direction and including a stair step structure having steps comprising edges of a group of the conductive structures within a vertical span of the vertically extending strings of non-volatile memory cells;
- and
- conductive contact structures within a horizontal area of the stair step region of the stack structure, the conductive contact structures individually physically contacting a respective one the steps of the stair step structure and electrically coupled to circuitry configured to operate the vertically extending strings of non-volatile memory cells.
3 more elements
A 3D NAND Flash memory device, comprising:
- a stack structure including levels of conductive material vertically interleaved with levels of dielectric structures, the stack structure including:
- a first stair step structure having positive slope and including first steps comprising first horizontal ends of at least some of the levels of conductive material;
- and
- a second stair step structure having negative slope and including second steps comprising second horizontal ends of the at least some of the levels of conductive material;
- first conductive contacts within a horizontal area of the first stair step structure and contacting at least some of the first steps;
- second conductive contacts within a horizontal area of the second stair step structure and contacting at least some of the second steps;
- and
- vertically extending strings of memory cells within a vertical span of the stack structure.
5 more elements
Dependencies are inferred from the claim text.