Circuit input/output (i/o) test system

A method for testing a circuit, the method comprising:

• providing a set of system-on-chip (SoC) scan data to a scan input terminal of the circuit generated from an automatic test pattern generator (ATPG);
• shifting the set of SoC scan data through scan-chain registers in response to a scan enable signal and a scan clock signal that are each associated with propagating the SoC scan data through the circuit to provide a predetermined initial device state of a circuit core of the circuit;
• alternately switching a bidirectional input/output (I/O) control of each of a plurality of bidirectional I/O circuits between an input mode and an output mode at each shift of the set of SoC scan data via the scan enable signal and the scan clock signal subsequent to the predetermined initial device state;
• providing input parametric testing of an I/O pad of each of the respective bidirectional I/O circuits in the input mode via a pin parametric measurement unit (PPMU);
• and
• providing output parametric testing of the I/O pad of each of the respective bidirectional I/O circuits in the output mode via the PPMU.

A circuit comprising:

• a power terminal configured to receive input power to the circuit;
• a circuit core configured to perform an operational function;
• scan-chain registers configured to propagate a set of system-on-chip (SoC) scan data that is input to the circuit from an automatic test pattern generator (ATPG) to set a different device state of the circuit core at each shift of the SoC scan data;
• and
• a plurality of bidirectional input/output (I/O) circuits each comprising a bidirectional I/O control, an I/O pad, and testing logic, the testing logic being configured to facilitate input and output parametric testing of the I/O pad via the respective bidirectional I/O control by a pin parametric measurement unit (PPMU) concurrently with a quiescent current measurement test of the power terminal by a digital power supply (DPS) at each shift of the set of SoC scan data.

A method for testing a circuit, the method comprising:

• coupling a digital power supply (DPS) to a power terminal of the circuit;
• providing a set of system-on-chip (SoC) scan data to a scan input terminal of the circuit from an automatic test pattern generator (ATPG);
• shifting the set of SoC scan data through scan-chain registers in response to a scan enable signal and a scan clock signal that are each associated with propagating the SoC scan data through the circuit to provide a predetermined initial device state of a circuit core of the circuit;
• providing a parametric test of an input/output (I/O) pad of each of a plurality of bidirectional I/O circuits via a pin parametric measurement unit (PPMU) at each shift of the set of SoC scan data via the scan enable signal and the scan clock signal subsequent to the predetermined initial device state;
• and
• providing a quiescent current measurement test of the power terminal via the DPS concurrently with the parametric test of the respective I/O pad of each of the bidirectional I/O circuits at each shift of the set of SoC scan data.

A circuit comprising:

• a bidirectional control switching network having a first input, a second input, a third input, and a plurality of outputs, the first input of the bidirectional control switching network being adapted to receive a set of SoC scan data, the second input of the bidirectional control switching network being adapted to receive a scan enable signal, and the third input of the bidirectional control switching network being adapted to receive a scan clock signal;
• and
• a plurality of bidirectional I/O circuits, each of the bidirectional input/output (I/O) circuits comprising:
• a sense and drive-back network having a first input, a second input, a third input, a fourth input, and an output, the first input of the sense and drive-back network being adapted to receive the set of SoC scan data, the second input of the sense and drive-back network being adapted to receive the scan enable signal, and the third input of the sense and drive-back network being adapted to receive the scan clock signal;
• and
• a bidirectional I/O control having a first input, a second input, an output, and an I/O pad, the first input of the bidirectional I/O control being coupled to one of the plurality of outputs of the bidirectional control switching network, the second input of the bidirectional I/O control being coupled to the output of the sense and drive-back network, and the output of the bidirectional I/O control being coupled the fourth input of the sense and drive-back network.