Polyphase Filter Banks with Rational Decimation / Interpolation Factor
AssigneeRamon Space Ltd.
InventorsHai Morgenstern, Eviatar Ohayon
Life of this patent
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Abstract
An Analysis Polyphase Filter (APPF) for shifting a selected passband of an input signal to a passband signal, having a Q=M·B/A decimation factor, B and A being co-primes, the APPF comprising M·B Paths. Each path includes (i) M·B/A multiplication Sub-paths, and (ii) a Sub-path Fusion Circuit, which is configured to generate fused multiplication products responsively to a sum of the multiplication n products generated by each of the multiplication sub-paths.
Claims12
An Analysis Polyphase Filter (APPF) for shifting a selected passband of an input signal to a passband signal, having a Q=M·B/A decimation factor, B and A being co-primes, the APPF comprising M·B Paths, each path comprising (i) M·B/A multiplication Sub-paths, and (ii) a Sub-path Fusion Circuit, which is configured to generate fused multiplication products responsively to a sum of the multiplication products generated by each of the multiplication sub-paths.
A Synthesis Polyphase Filter (SPPF) for shifting a baseband signal to a passband of an output signal, having a Q=M·B/A interpolation factor, B and A being co-primes, the SPPF comprising (i) M·B Paths, each path comprising M·B/A multiplication Sub-paths, and (ii) a Sub-path Expansion Circuit, which is configured to split multiplication products from the multiplication sub-paths.
A Channelizer for shifting a passband in an input signal to a baseband signal, the channelizer comprising an Analysis polyphase Filter (APPF), having a Q=M·B/A decimation/interpolation factor, B and A being co-primes, the APPF comprising M·B Paths, each path comprising (i) M·B/A multiplication Sub-paths and (ii) a Sub-path Fusion Circuit, which is configured to generate fused multiplication products responsively to a sum of the multiplication products generated by each of the multiplication sub-paths.
An Up-Converter for shifting a baseband signal to a passband within an output signal, the Up-Converter comprising a Synthesis Polyphase Filter (SPPF), having a Q=M·B/A decimation/interpolation factor, B and A being co-primes, the SPPF comprising M·B Paths, each path comprising (i) M·B/A multiplication Sub-paths and (ii) a Sub-path Expansion Circuit, which is configured to split multiplication products from the multiplication sub-paths.
Dependencies are inferred from the claim text.