Electronic chip comprising stressed transistors
AssigneeSTMicroelectronics International N.V.
InventorsRemy BERTHELON, Olivier WEBER
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AssigneeSTMicroelectronics International N.V.
InventorsRemy BERTHELON, Olivier WEBER
Estimating the term…
The present description concerns a method of manufacturing an electronic chip comprising the successive steps of: providing a semiconductor layer located on an insulator covering a semiconductor substrate; oxidizing first and second portions of the semiconductor layer down to the insulator, to form first oxidized portions and second oxidized portions on the insulator; generating stress in a third portion of the semiconductor layer through which the first and second oxidized portions do not pass, the third portion continuously extending between the second oxidized portions; forming cavities extending at least down to the semiconductor substrate through the second oxidized portions and the insulator; and forming first field-effect transistors in and on top of the third portion.
A method of manufacturing an electronic chip, comprising:
An electronic chip, comprising:
A device, comprising:
Dependencies are inferred from the claim text.