Memory device and method for forming the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsJi-Kuan LEE, Min-Chiao YEH, Yao-Jen YANG, Gu-Huan LI, Chen-Wei LIANG
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Abstract
A method includes forming a first select transistor of a first one-time programmable (OTP) memory bit cell over a substrate, wherein the first select transistor is of a first conductivity type; forming a first anti-fuse transistor of the first OTP memory bit cell over the substrate, wherein the first anti-fuse transistor is of a second conductivity type opposite to the first conductivity type; forming a bit line over the substrate, wherein the bit line is electrically coupled to a source/drain terminal of the first select transistor.
Claims20
A method, comprising:
- forming a first select transistor of a first one-time programmable (OTP) memory bit cell over a substrate, wherein the first select transistor is of a first conductivity type;
- forming a first anti-fuse transistor of the first OTP memory bit cell over the substrate, wherein the first anti-fuse transistor is of a second conductivity type opposite to the first conductivity type;
- and
- forming a bit line over the substrate, wherein the bit line is electrically coupled to a source/drain terminal of the first select transistor.
A method, comprising:
- forming a first active region over a substrate, and a second active region over the substrate;
- forming a plurality of first source/drain regions on the first active region, and a plurality of second source/drain regions on the second active region;
- forming a first gate structure around the first active region and between the first source/drain regions, wherein the first gate structure forms an n-type metal-oxide-semiconductor (NMOS) transistor with the first source/drain regions, and the NMOS transistor is of an one-time programmable (OTP) memory bit cell;
- and
- forming a second gate structure around the second active region and between the second source/drain regions, wherein the second gate structure forms a p-type metal-oxide-semiconductor (PMOS) transistor with the second source/drain regions, and the PMOS transistor is of the OTP memory bit cell.
A semiconductor structure, comprising:
- a substrate;
- a select n-type metal-oxide-semiconductor (NMOS) transistor over the substrate;
- a programming NMOS transistor over the substrate;
- and
- a first programming p-type metal-oxide-semiconductor (PMOS) transistor over the substrate, wherein the select NMOS transistor, the programming NMOS transistor, and the programming PMOS transistor form an one-time programmable (OTP) memory bit cell.
Dependencies are inferred from the claim text.