US 2025/0226818 A1 · Techniques For Routing Between A Network-On-Chip And Multiplexer Circuits In A Central Region Of An Integrated Circuit

Abstract

An integrated circuit includes a central region having first multiplexer circuits and first busses that interconnect the first multiplexer circuits. The integrated circuit also includes a network-on-chip. The network-on-chip includes switch circuits, second multiplexer circuits, second busses that interconnect the switch circuits, third busses that interconnect the switch circuits and the second multiplexer circuits, and fourth busses that interconnect the first multiplexer circuits and the second multiplexer circuits. Each of the second multiplexer circuits is coupled to at least two of the switch circuits through a subset of the third busses.

Claims20

Dependent claims

An integrated circuit comprising:

a central region comprising first multiplexer circuits and first busses that interconnect the first multiplexer circuits;
and
a network-on-chip comprising switch circuits, second multiplexer circuits, second busses that interconnect the switch circuits, third busses that interconnect the switch circuits and the second multiplexer circuits, and fourth busses that interconnect the first multiplexer circuits and the second multiplexer circuits, and wherein each of the second multiplexer circuits is coupled to at least two of the switch circuits through a subset of the third busses.

A method for providing an integrated circuit that is configurable to bypass a portion of a network-on-chip to reduce routing congestion, the method comprising:

providing a central region in the integrated circuit, wherein the central region comprises first multiplexer circuits and first busses that couple together the first multiplexer circuits;
and
providing the network-on-chip in the integrated circuit, wherein the network-on-chip comprises switch circuits, second multiplexer circuits, second busses that couple together the switch circuits, third busses that couple the switch circuits to the second multiplexer circuits, and fourth busses that couple the first multiplexer circuits to the second multiplexer circuits, and wherein each of the second multiplexer circuits is configurable to couple together at least two of the switch circuits through at least two of the third busses.

Dependencies are inferred from the claim text.

Techniques For Routing Between A Network-On-Chip And Multiplexer Circuits In A Central Region Of An Integrated Circuit

Life of this patent

Techniques For Routing Between A Network-On-Chip And Multiplexer Circuits In A Central Region Of An Integrated Circuit

Life of this patent

Abstract

Claims20