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US 2025/0226014 A1Published application
Output latch and amplifier
AssigneeNVIDIA Corporation
InventorsLalit Gupta, Jason Golbus, Jesse San-Jey Wang
Life of this patent
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Abstract
Readout logic for bit-storing cells of a machine memory wherein the bit-storing cells comprise first read/write voltage domain crossings includes a read latch coupled to the bit-storing cell via a read bitline and the read latches include second read/write voltage domain crossings configured in pull-down networks of the read latches.
Claims20
A circuit comprising:
- a bit-storing cell comprising a first read/write voltage domain crossing;
- a read latch coupled to the bit-storing cell via a read bitline;
- and
- the read latch comprising a second read/write voltage domain crossing.
1 more element
The circuit of claim 7, wherein the first read/write voltage domain crossing is configured at an interface of the bit-storing cell to the read bitline.
A circuit comprising:
- a bit-storing cell configured to operate in a write voltage domain;
- a read latch coupled to the bit-storing cell via a read bitline, the read bitline configured to operate in a read voltage domain different than the write voltage domain;
- and
- a first read/write voltage domain crossing configured in the read latch.
1 more element
A memory system comprising:
- a memory bank comprising a plurality of bit-storing cells operating in a write voltage domain;
- the bit-storing cells coupled to a read bitline operating in a read voltage domain different than the write voltage domain;
- a read latch coupled to the read bitline;
- a keeper circuit coupled between the read bitline at a latching node of the read latch;
- and
- a first read/write voltage domain crossing coupled to the latching node.
3 more elements
A process comprising:
- configuring a bit-storing cell to operate in a write voltage domain of a memory circuit;
- configuring a read latch coupled to the bit-storing cell via a read bitline to operate in a read voltage domain different than the write voltage domain;
- and
- configuring a read/write voltage domain crossing in the read latch.
1 more element
Dependencies are inferred from the claim text.