Methods and neural network accelerators for executing a dynamic neural network

A method of processing a dynamic neural network at a neural network accelerator comprising one or more hardware accelerators, an embedded processor, and a command decoder, the method comprising, at the command decoder:

• controlling the one or more hardware accelerators and the embedded processor in accordance with commands of a command stream;
• in response to determining that the command stream comprises a set of one or more branch commands that indicate that a conditional branch is to be performed, cause the embedded processor to determine a next command stream;
• and
• in response to receiving information, via the hardware feedback path, from the embedded processor identifying the next command stream, controlling the one or more hardware accelerators and the embedded processor in dependence on the commands of the next command stream.

A non-transitory computer readable storage medium having stored thereon a computer readable dataset description of a neural network accelerator that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture an integrated circuit embodying a neural network accelerator comprising:

• one or more hardware accelerators, each hardware accelerator configured to accelerate one or more neural network operations;
• an embedded processor;
• a command decoder configured to process commands from a command stream;
• and
• a hardware feedback path between the embedded processor and the command decoder, wherein the hardware feedback path is configured to enable the embedded processor to notify the command decoder of which command stream the command decoder is to process next;
• wherein the command decoder of at least a first neural network accelerator core of the one or more neural network accelerator cores is configured to:
• i) control the one or more hardware accelerators and the embedded processor of that core in accordance with commands of a command stream;
• ii) in response to processing a command stream comprising a set of one or more branch commands that indicate a conditional branch is to be performed, cause the embedded processor to determine a next command stream, and
• iii) in response to receiving information, via the hardware feedback path, from the embedded processor identifying the next command stream, control the one or more hardware accelerators and the embedded processor in dependence on the commands of the next command stream.