Driving analog compute-in-memory cells using low power sparsity-aware digital-to-analog converters
AssigneeIntel Corporation
InventorsHechen Wang, Renzhi Liu, Richard Dorrance, Brent Carlton
Life of this patent
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AssigneeIntel Corporation
InventorsHechen Wang, Renzhi Liu, Richard Dorrance, Brent Carlton
Estimating the term…
Some challenges to using analog compute-in-memory circuits for machine learning hardware relate to the overhead and non-idealities associated with data converters at the input and output of the analog compute-in-memory circuits. To address at least some of these challenges, a digital-to-analog converter having binary-weighted resistances can be used to drive the analog compute-in-memory circuits. The resulting digital-to-analog converter is sparsity-aware with low average power consumption. A calibration engine can perform analog tuning and/or digital post-correction to mitigate the non-idealities of the digital-to-analog converter.
An apparatus, comprising:
A method, comprising:
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